1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, more particularly, to data read operation in a non-volatile semiconductor memory device designed to store data by charge accumulation on floating gates, such as a flash memory.
2. Description of the Related Art
In general, a non-volatile semiconductor memory device configured to store data by charge accumulation on floating gates of memory cell transistors, such as a flash memory, uses reference cells in data read operations from memory cells. Most typically, reference cells are used to generate a reference current, and data stored in the selected memory cell are identified by comparing the cell current obtained from the memory cell with the reference current. It should be noted that, in this specification, the “floating gate” means to include not only a floating gate formed of conductive material but also that formed of insulating material over which charges are accumulated, such as a MONOS cell (metal-oxide-nitride-oxide-semiconductor cell).
Japanese Laid Open Patent Application No. JP-A Heisei, 8-190797 discloses a non-volatile semiconductor memory device which uses reference cells for data read operations from memory cells. FIG. 1 shows the configuration of the non-volatile semiconductor memory device disclosed in this patent application. The disclosed non-volatile semiconductor memory device is provided with memory cells 102 having floating gates, reference cells 116a, 116b, wordines 118 and bitlines 122. The wordlines 118 are connected to a column decoder 120, and the bitlines 122 are connected to a row decoder 124. A write voltage drive circuit 126 is connected to the row decoder 124, and a read voltage drive circuit 128 is connected to the column decoder 120 and the row decoder 124. The voltages used for programming and erasing the memory cells 102 are supplied to the row decoder 124 by the write voltage drive circuit 126, and the voltages required used for reading data from the memory cells 102 are supplied to the column decoder 120 and the row decoder 124 by the read voltage drive circuit 128.
In the non-volatile semiconductor memory device shown in FIG. 1, two reference cells 116a and 116b are connected to each wordline 118. One of the two reference cells 116a and 116b is placed into the “programmed” state, and the other is placed into the “erased” state. In the read operation, a desired wordline 118 is selected, and currents i0 and i1 flowing through the two reference cells 116a and 116b connected to the selected word line 118 are used to generate a reference current ire. In detail, the currents i0 and i1 flowing through the reference cells 116a and 116b are subjected to current calculation with converting circuits 130, 132, an adder circuit 134 and a converting circuit 136, and the reference current ire is thereby generated so as to have an intermediate current level between those of the currents i0 and i1. The data stored in the memory cell 102 are identified by comparing the cell current flowing through the memory cell 102 with the reference current ire by using a differential amplifier 138.
The non-volatile semiconductor memory device shown in FIG. 1 suffers from the following three problems:
First, the non-volatile semiconductor memory device shown in FIG. 1 suffers from the increase in the scale of the read circuitry. In the non-volatile semiconductor memory device shown in FIG. 1, two reference cells respectively placed in the “programmed” and “erased” states are connected to each wordline. This undesirably increases the number of the reference cells and increases the scale of the read circuitry. In addition, the non-volatile semiconductor memory device shown in FIG. 1 requires various circuits for generating the intermediate level current having a current level between those of the currents obtained from the “programmed” and “erased” reference cells, including the converting circuit 130, the converting circuit 132, the adder circuit 134 and the converting circuit 136. This also increases the scale of the read circuitry.
Second, the non-volatile semiconductor memory device shown in FIG. 1 suffers from the complicated operation sequence and/or circuit configuration. The non-volatile semiconductor memory device shown in FIG. 1, which incorporates both of “programmed” and “erased” reference cells, requires the programming operation for the “programmed” reference cell before the read operation from the memory cell 102. This undesirably complicates the operation of the memory device. In addition, the non-volatile semiconductor memory device shown in FIG. 1 requires a special operation sequence and/or circuit configuration in order to keep the “programmed” reference cell in the “programmed” state. For example, when “programmed” reference cells are formed within the same well as the memory cells 102, a programming operation is required for the “programmed” reference cells after the erasing operation for the memory cells 102. This undesirably makes the operation sequence complicated. Forming “programmed” reference cells within a different well from the memory cells 102 may avoid the complicated operation sequence; however, this undesirably makes the circuit configuration of the non-volatile semiconductor memory device complicated.
Finally, the non-volatile semiconductor memory device shown in FIG. 1 actually suffers from the poor adjustability of the reference current. In the non-volatile semiconductor memory device in FIG. 1, the reference current may be adjusted by changing the magnifications of the converting circuits 130, 132 and 136; however, this approach is not preferable from the viewpoint of the actual implementation. For example, when current mirrors are used as the converting circuits 130, 132 and 136, the control of the mirror ratios may be achieved by using transistors with different gate widths. This approach, however, undesirably requires integrating an increased number of transistors with different gate widths in order to finely adjust the reference current, causing the increase in the circuit scale. The reduction of the circuit scale may be achieved by reducing the number of the transistors prepared for the current mirrors; however, this approach makes it impossible to finely adjust the reference current.